Testing apparatus

ABSTRACT

A testing apparatus including a plurality of testing module slots to which different types of testing modules for testing a device under test are optionally mounted, includes operation order holding means for holding information indicating that a test operation by a first testing module among the plurality of testing modules should be performed before a test operation by a second testing module among the plurality of testing modules, trigger return signal receiving means for receiving a trigger return signal from the first testing module, the trigger return signal indicating that the first testing module has completed the test operation thereof, when the test operation of the first testing module has been completed, and trigger signal supplying means for supplying a trigger signal to the second testing module, the trigger signal indicating that the second testing module should start the test operation thereof, when the trigger return signal receiving means receives the trigger return signal.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a testing apparatus. More particularly,the present invention relates to a testing apparatus including aplurality of testing module slots to which different types of testingmodules are optionally mounted.

2. Description of the Related Art

A testing apparatus for performing an analog test of a device under testperforms the test by allowing one testing module to generate and supplya test signal to the device under test and another testing module tomeasure the output signal from the device under test. In order torealize the operations of such testing modules, the testing apparatuscontrols the testing modules synchronously, while supplying triggersignals to them based on a testing program which determines testsequences such as the operation order of the testing modules.

Recently, a testing apparatus including a plurality of testing moduleslots to which different types of testing modules for generatingdifferent types of test signals for the test of the device under testrespectively are optionally mounted has been developed. In such testingapparatus, since the testing modules mounted to the plurality of testingmodule slots respectively are optionally changed, and the times requiredfor the test operations for the test modules are different from eachother, it is inevitable to make a testing program which corresponds tothe mounting positions or the combination of the testing moduleswhenever the testing modules are changed, and it is necessary to preparea process for a extremely difficult test.

SUMMARY OF THE INVENTION

Therefore, it is an object of the present invention to provide a testingapparatus, which is capable of overcoming the above drawbacksaccompanying the conventional art. The above and other objects can beachieved by combinations described in the independent claims. Thedependent claims define further advantageous and exemplary combinationsof the present invention.

According to the first aspect of the present invention, a testingapparatus including a plurality of testing module slots to whichdifferent types of testing modules for testing a device under test areoptionally mounted, includes operation order holding means for holdinginformation indicating that a test operation by a first testing moduleamong the plurality of testing modules should be performed before a testoperation by a second testing module among the plurality of testingmodules, trigger return signal receiving means for receiving a triggerreturn signal from the first testing module, the trigger return signalindicating that the first testing module has completed the testoperation thereof, when the test operation of the first testing modulehas been completed, and trigger signal supplying means for supplying atrigger signal to the second testing module, the trigger signalindicating that the second testing module should start the testoperation thereof, when the trigger return signal receiving meansreceives the trigger return signal.

The first testing module may be an arbitrary waveform adjustor forgenerating and supplying an arbitrary analog waveform to the deviceunder test, the second testing module may be a phase characteristicstester for receiving an analog waveform outputted by the device undertest in response to the analog waveform supplied from the arbitrarywaveform adjustor, and testing phase characteristics of the analogwaveform, the operation order holding means may hold informationindicating that the phase characteristics tester should perform areceiving operation of the analog waveform from the device under test,after the arbitrary waveform adjustor performs a supply operation of theanalog waveform to the device under test, the trigger return signalreceiving means may receive the trigger return signal from the arbitrarywaveform adjustor, the trigger return signal indicating that thearbitrary waveform adjustor has completed the supply operation, when thesupply operation at a predetermined time of the analog waveform hascompleted by the arbitrary waveform adjustor, and the trigger signalsupplying means may supply the trigger signal to the phasecharacteristics tester, the trigger signal indicating that, the phasecharacteristics tester should start the receiving operation of theanalog waveform from the device under test, when the trigger returnsignal receiving means receives the trigger return signal.

The trigger return signal receiving means and the trigger signalsupplying means may be a multiplexer circuit for obtaining each of aplurality of the trigger return signals from each of the plurality oftesting modules, selecting one of the trigger return signals obtainedfrom the first testing module, and supplying the selected trigger returnsignal to the second testing module as the trigger signal, and theoperation order holding means may be a flip-flop circuit for holding aselect signal for controlling the multiplexer circuit to select thetrigger return signal.

The first testing module may perform first and second test operations inparallel, the operation order holding means may hold informationindicating that the test operation by the second testing module shouldbe performed after the first test operation by the first testing module,and information indicating that a test operation by a third testingmodule among the plurality of testing modules should be performed afterthe second test operation by the first testing module, the triggerreturn signal means may receive a first trigger return signal from thefirst testing module, the first trigger return signal indicating thatthe first testing module has completed the first test operation, whenthe first test operation of the first testing module has been completed,and a second trigger return signal from the first testing module, thesecond trigger return signal indicating that the first testing modulehas completed the second test operation, when the second test operationof the first testing module has been completed, and the trigger signalsupplying means may supply a first trigger signal to the second testingmodule, the first trigger signal indicating that the second testingmodule should start the test operation thereof, when the trigger returnsignal receiving means receives the first trigger return signal, and asecond trigger signal to the third testing module, the second triggersignal indicating that the third testing module should start the testoperation thereof, when the trigger return signal receiving meansreceives the second trigger return signal.

The summary of the invention does not necessarily describe all necessaryfeatures of the present invention. The present invention may also be asub-combination of the features described above. The above and otherfeatures and advantages of the present invention will become moreapparent from the following description of the embodiments taken inconjunction with the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is an example system block diagram

FIG. 2 is an example test head layout for 4 DUT testing

FIG. 3.1 is an example system synchronization block diagram

FIG. 3.2 is an example ASYNC module block diagram

FIG. 4.1 is a pictorial view of exemplary RF load board

FIG. 5.1 is an example RF instrument showing modules for 4 DUT paralleltesting

FIG. 5.2 is an example VSA/VSG module

FIG. 5.3 is a computing architecture: VSA/VSG bus connection

FIG. 5.4 is an example RFCOM module block diagram

FIG. 5.5 is an example RFDIST block diagram

FIG. 5.6 is an example block diagram of RFFE (RF front end)

FIG. 5.7 is an example RFMTX block diagram

FIG. 5.8 is an example time analysis for sequential DUT digitizing for 4DUTs

FIG. 6.1 is an example BBFE module block diagram

FIG. 7.1 is an example BBWG/D block diagram

FIG. 8.1 is an example AVWG/D block diagram

FIG. 9.1 is an exemplary block diagram of 250M digital module showingDCAP and DAW

FIG. 10 shows an example of the configuration of a testing apparatus 100related to an exemplary embodiment of the present invention.

FIG. 11 shows an example of the detailed configuration of a testingapparatus 100 related to this embodiment.

FIG. 12 shows an example of the operation sequence of a testingapparatus 100 related to this embodiment.

FIG. 13 shows an example of the configuration of a trigger matrix 206related to this embodiment.

DETAILED DESCRIPTION OF THE INVENTION

The invention will now be described based on the preferred embodiments,which do not intend to limit the scope of the present invention, butexemplify the invention. All of the features and the combinationsthereof described in the embodiment are not necessarily essential to theinvention.

1. Introduction

The present invention is directed to a group of test head modulesdesigned to perform RF and mixed-signal/analog testing when installed inthe test head of systems such as the Semiconductor Test Consortium (STC)OPENSTAR compliant test system. These modules are designed to enabletesting of devices that include, but are not limited to, W-LAN, cellphone, audio, video, disk drive, HDTV, DVD, and other RF, analog, andmixed-signal integrated circuits.

The test head modules described herein include the following: ASYNCAnalog Sync RF Modules VSA/VSG Vector Signal Analyzer/Vector SignalGenerator RF COM RF Common RF DIST RF Distribution RF FE RF Front End RFMTX RF Switch Matrix RFPA RF Power Amplifier AVWG/D Audio Video WaveformGenerator/Digitizer BBWG/D Base Band Waveform Generator/Digitizer BBFEBase Band Front end

The following description covers exemplary architecture, physicalcharacteristics, and specifications for each test head module. The RFmodules listed above are sub instruments, designed to be interconnectedto form a complete test instrument. In this case, some specificationsapply only to the complete test instrument. Note that although exemplaryarchitectures, physical characteristics, and specifications of thepresent invention are described for purposes of illustration andexplanation, embodiments of the present invention are not limited to theexamples disclosed herein.

Additionally, this document contains information on RF calibration, themixed-signal portions of a 250 MHz digital module, computer connectionsto the RF subsystem, Device Interface, RF and mixed-signal software, andparallel testing.

2. System Overview

Many test system configurations are possible using the modules describedherein. An example application configuration pictured below shows theinterconnection of the RF modules to form a complete RF instrument, andshows 4 DUT parallel testing, using waveform generator/digitizer modulesto provide additional signals to the DUTs.

2.1 Example Application Configuration

The block diagram for an example system configuration is shown in FIG.2.1. The system is configured to test four DUTs, for example, multi-bandcell phone RF chips. A brief description of the modules and signal flowis given below. A more detailed description of each module and itsoperation appears in section 5 through 9.

During testing, a modulated RF signal generated by the Vector SignalGenerator is sent to the RFCOM module where, depending on the test, itmay be combined with a signal from a 6 GHz CW Signal Generator (CWSG6G),amplified, and/or low pass filtered. The signal then goes to the RFDISTModule, where it gets distributed to four RF Front End Modules, one foreach DUT. The RF Front End Modules provide directional couplers andmixers for direct digital measurement of forward and reflected power bymeans of the system digitizers. A second 6 GHz CW Signal Generator(CWSG6G) on the RF COM Module provides the system local oscillatorsignal for the mixers on the RF Front End Modules. A third 6 GHz CWSignal Generator (CWSG6G) on the RF COM Module provides a localoscillator signal for the DUT. This signal is distributed to four RFFEmodules by the RFDIST module. Both the DUT local oscillator andmodulated RF signals are sent from the RFFE module to the RFMTX module.The RFMTX module switches the modulated RF signal to one of fouroutputs. The RF MTX also switches the DUT local oscillator signal to oneof two outputs, and provides connections through the RF HIFIX to theDUT. RF signals from the DUT are switched by the RFMTX and sent to theRFFE module, where they may be down-converted and sent to a digitizer(through the BBFE), or where they may be sent on to the Vector SignalAnalyzer by way of the VSA Selector on the RFCOM module.

Base band signals are passed through the BBFE module to and from one ofthe waveform generator/digitizers in the test head, in this case theRBWG/D on the VSG/VSA module.

2.2 Physical Configuration

FIG. 2.2 shows a possible test head module layout for testing four DUTsin parallel, where each DUT may require RF, base band, digital, andaudio frequency input and output signals. This configuration could beused for the example system pictured in FIG. 2.1.

In one embodiment of the present invention, the VSG/VSA Module requires11 physical test head slots. (A single physical test head slot is 24 mmwide, as defined by the STC OPENSTAR Architecture Specification.) Inanother embodiments, the RF COM Module requires 9 physical test headslots. Both of these modules are comprised of sub-modules mounted inchassis that fit into the test head. The other modules shown eachrequire one 24 mm test head slot.

3. Analog Sync

The analog sync, or ASYNC, module synchronizes the RF and analog modulesin the system by means of trigger and clock lines that are connected toeach module. Additionally, the ASYNC module synchronizes the RF andanalog modules with the digital subsystem. The analog sync module alsosupplies a low phase noise reference clock to the entire system.

In embodiments of the present invention, each ASYNC Module must have itsown site controller. In embodiments of the present invention, up to twoASYNC Modules may be connected together in the test head. In embodimentsof the present invention, additional ASYNC modules or pairs of modulesmust operate independently.

3.1 Analog Sync Description

FIG. 3.1 shows an example system synchronization block diagram. Eachanalog sync module can control up to 16 RF/analog modules. It can alsosynchronize with the digital modules through the pattern CONTINUE inputon the Sync Matrix, and by means of logic synchronized signals from theoptional LSYNC Module or from the digital modules, connected through theperformance board.

The analog sync module contains a low phase noise 100 MHz referenceclock. When the ASYNC Module is present in a system, this referencebecomes the master reference for the entire system. The 100 MHzreference clock is sent directly to all the RF/analog modules. Inaddition, a 10 MHz reference clock derived from the 100 MHz reference issent to the SYNC Matrix Modules to control the 250 MHz reference clockon these modules.

An exemplary block diagram of the ASYNC Module is shown in FIG. 3.2.Table 3.1 shows the number of clock and trigger lines that are connectedto each RF/analog module. TABLE 3.1 Number of Clock and Trigger Lines toEach RF/Analog Module ANALOG REFERENCE CLOCK 1 ANALOG CLOCK 2 ANALOGTRIGGER SEND 4 ANALOG TRIGGER RETURN 2 CONTROL SIGNAL 1

The ASYNC module contains a 1 KHz to 500 MHz variable clock source thatis available to all the RF/analog modules. Pattern controlled clocks canbe generated through the LSYNC clock connection.

3.2 Example ASYNC Module Specifications

Table 3.2 lists the exemplary ASYNC Module specifications. TABLE 3.2Example ASYNC Module Specifications Feature Specification DetailsReference CLOCK Frequency 100 MHz Frequency stability <±1 ppm Phasenoise −140 dBc/Hz @ 10 kHz Variable CLOCK Frequency range 1 kHz to 500MHz Frequency resolution <1 Hz Spurious level −60 dBc Phase noise −90dBc/Hz @ 10 kHz Number of CLOCK/TRIGGER 16 PortsPB Trigger4. Device Interface

Most of the analog modules connect to the DUT through the same type ofconnections on the HIFIX and Load Board as used by the digital modules.A 120 pin connector at the top of the module mates with a cable mountedconnector assembly on the HIFIX. Then the signals are cabled up to aconnector at the Load Board interface. (See Open Architecture HardwareSpecification.)

The connection system described above is not suitable for the RFsubsystem. An RF HIFIX and RF Load Board may be developed to connect theRF subsystem to a DUT. Connections are made through a series of blindmate coaxial connectors at the end of the RF module, SMA connectedsemi-rigid coax, blind mate coaxial connectors at the Load Boardinterface, and semi-rigid coax to an SMA connector near the DUT. FIG.4.1 shows a pictorial of the RF Load Board and DUT connections.

5. RF Modules

The RF modules in Table 5.1 are connected together to form a complete RFinstrument. RF calibration treats the entire instrument as a single unit(with the exception of calibration factors for the load board), sinceintermediate points are not always accessible for calibration. Somespecifications are given for individual modules, but the completeinstrument specification, given in section 5.7, defines the performanceof the complete RF instrument. TABLE 5.1 RF modules which form thecomplete RF instrument VSA/VSG Vector Signal Analyzer/Vector SignalGenerator RF COM RF Common RF DIST RF Distribution RF FE RF Front End RFMTX RF Switch Matrix RFPA RF Power Amplifier

FIG. 5.1 shows the complete RF instrument. The individual modules aredescribed below.

5.1 VSA/VSG Module

The VSA/VSG is the Vector Signal Analyzer/Vector Signal Generator.

5.1.1 VSA/VSG Description

FIG. 5.2 shows an exemplary block diagram of the VSA/VSG Module.

The VSG generates CW or modulated RF waveforms from 50 MHz to 6 GHz. TheRBWG (RF Base band Waveforn Generator) contains two 14 bit 200 MS/sarbitrary waveform generators to generate I (in phase) and Q(quadrature) base band modulation signals. The RFUPC (RF Upconverter)converts the base band signals to an I/Q modulated RF waveform in thefrequency range of 50 MHz to 6 GHz. The RBWG I and Q outputs are alsoavailable to send to the DUT through the BBFE module (see section 6).

The VSA analyzes modulated RF signals by downconverting them to IF(using the RFDWC, or RF Downconverter) and digitizing them with a 14 bit100 MS/s digitizer (part of the RBWD, or RF Base band Digitizer). Thedigitized waveforms are digitally downconverted to base band beforebeing stored in the 32 MW digitizer memory, to be passed to a computerfor analysis.

The VSA allows modulation analysis of signals in the 50 MHz to 6 GHzfrequency range. In addition, the VSA can operate as a spectrum analyzerfrom 20 Mhz to 18 GHz.

In embodiments of the present invention, the RBWD contains two separate14 bit 100 MS/s digitizers. I and Q inputs to the RBWD are availablethrough the BBFE module (see section 6) to digitize base band signalsfrom the DUT.

5.1.2 VSA/VSG Data Bus

The VSA/VSG Module uses both the primary Open Architecture Fiber Channeldata bus and the optional StarGen StarFabric-bridged PCI bus. Datatransfer from the RBWG/D memories to the site controller CPU is throughthe PCI bridge. FIG. 5.3 shows these bus connections in relation to anexemplary computing architecture.

5.1.3 VSA/VSG Physical

In one embodiment of the present invention, the VSA/VSG requires 11 STCOpen Architecture 24 mm test head slots.

5.1.4 Example VSA/VSG Specifications

Tables 5.2 and 5.3 show exemplary specifications for one embodiment ofthe VSA/VSG module. However, it should be noted that other embodimentsmay have other specifications and conditions. TABLE 5.2 Example VSASpecifications Items Specification Conditions VSA RFDWC Frequency Ranges20 MHz˜18 GHz Spectrum Analyzer Requires Coax Sw on RFMTX, SEL 50 MHz˜6GHz Modulation Analyzer Input Power Level −120 dBm˜20 dBm Through RFMTX,RFFE, and RFCOM Power Meas. Accuracy +/−1 dB@−30 dBm˜0 dBm ThroughRFMTX, RFFE, (init/oinit) and RFCOM Noise Floor −145 dBm/Hz typ ThroughRFMTX, RFFE, RBWD Number of channels 2ch and RFCOM Bandwidth (−3 dB) 40MHz Anti-aliasing filters 35 MHz and Digital Filter Input Voltage (max)−2.5 V to +2.5 V Through BBFE Sampling rate 100 MS/s Memory 32 MW/chNumber of bits 14 bits Digital Modulation Analysis Spectrum, EVM,Constellation, Eye diagram . . .

TABLE 5.3 Example VSG Specifications. Items Specification Conditions VSGRFUPC Frequency Range 50 MHz˜6 GHz Freq. Resolution 0.1 Hz Output PowerLevel −120 dBm˜0 dBm (50 MHz˜2 GHz) At top of RF HIFIX, −120 dBm˜−5 dBm(2 GHz˜6 GHz) through RFFE Level Resolution 0.01 dB Accuracy (after +/−1dB@−30 dBm˜0 dBm At top of RF HIFIX, init/oinit) through RFFE PhaseNoise −115 dBc/Hz@6 GHz, 100 KHz Offset Output Impedance 50 ohm RBWGNumber of channels 2ch Frequency Range DC˜50 MHz Output Voltage (max) −2V to +2 V Through BBFE Sampling frequency 200 MS/s Number of bits 14bits Anti-aliasing filter 2.5 MHz/50 MHz/THROUGH Memory 64 MW/ch Max #of waveforms 64 Waveform length 1024 W to 64 MW Distortion −65 dBc at <5MHz Through BBFE −55 dBc at 5 MHz to 20 MHz Digital Communications GSM,cdma2000, WCDMA and 2G, Modulation standard 802.11a/b/g/h, HiperLAN2,HiSWANa Modulation GMSK, BPSK, QPSK, 16QAM, 64QAM, OFDM, CCK, etc . . .5.2 RFCOM Module

The RFCOM Module provides RF functions that are applied in common forall RFFE modules and all DUTs.

5.2.1 RFCOM Description

FIG. 5.4 shows an exemplary block diagram of the RFCOM module. The RFCOMmodule is comprised of three 6 GHz CW signal generators (CWSG6G), apower amplifier (PA), a two port RF combiner, generator low pass filters(Filt), and the receive selector switch (SEL). A trigger interface forthe RF instruments to the ASYNC module is also placed on the RFCOMmodule.

CWSG6G #1 provides a 50 Mhz to 6 GHz CW signal for two tone testing.When required, the signal from CWSG6G #1 is combined with the CW (ormodulated) signal from the VSG by the two port combiner to produce thetwo tone test signal. The power amplifier provides enough gain for thecomplete RF instrument to produce 0 dBm at the Load Board connectors. Atlower output levels the power amplifier is switched out. The Filt blockprovides switchable 1 GHz, 2 GHz, 3 GHz, and 6 GHz low pass filters toremove harmonics from the generator's output.

CWSG6G #2 provides a 50 MHz to 6 GHz local oscillator signal for theCoupler Receivers on the RFFE module. This signal is mixed with thesignals from the directional couplers on the RFFE module to produce baseband signals that can be digitized by a base band digitizer (such as theRBWD).

CWSG6G #3 provides a 50 MHz to 6 GHz CW signal to the DUT localoscillator port through the RFFE and the RFMTX modules.

The SEL block is a mechanical coaxial relay that selects which RFFEmodule will send its signal to the VSA. The mechanical relay provideslow insertion loss, giving better receiver sensitivity for low-levelmeasurements. Many tests are performed at higher signal levels and canuse the Coupler Receivers (see RFFE module, section 5.4) with theirelectronic switching for faster parallel DUT testing.

5.2.3 RFCOM Physical

In one embodiment of the present invention, the RFCOM module requires 9STC Open Architecture 24 mm test head slots.

5.2.4 Example RFCOM Specifications TABLE 5.4 Example CWSG6Gspecifications. Items Specification Conditions CWSG6G Frequency Range 50MHz˜6 GHz Freq. Resolution 1 Hz Output Power level −70 dBm˜0 dBm At topof HIFIX, through RFFE, RFMTX Level Resolution 0.1 dB Accuracy (after+/−0.8 dB@− At top of init/oinit) 30 dBm˜0 dBm HIFIX, through RFFE,RFMTX Phase Noise −115 dBc/Hz@6 GHz, 100 KHz Offset Output Impedance 50ohm

TABLE 5.5 Example Filt specifications. Items Specification Filt Cutofffrequencies 1 GHz, 2 GHz, 3 GHz, 6 GHz5.3 RFDIST Module

The RFDIST Module enables parallel DUT testing by distributing the RF,DUT local oscillator, and system local oscillator-signals to four RFFEmodules. If only a single RFFE module is used, the RFDIST module is notrequired.

5.3.1 RFDIST Description

FIG. 5.5 shows an exemplary block diagram of the RFDIST module. Thethree power dividers divide the RF, DUT local oscillator, and systemlocal oscillator signals each to 4 ports. Each of the power dividers hasan amplifier on each output port to compensate for the divider signalloss and to provide isolation between the ports. Thus, the conditions atone DUT do not affect the signals at the other DUTs during paralleltesting.

5.4 RFFE Module

The RFFE, or RF Front End, module provides directional couplers on eachDUT RF line to measure forward and reflected power, and to enable theCMR (Coupler-Mixer Receiver). Additional circuitry aids in calibrationand diagnostics. An optional noise source may be connected on the RFFEmodule for noise figure tests.

RFFE Description

FIG. 5.6 shows an exemplary block diagram of the RFFE module. The signalfrom the VSG, the signal to the VSA, and the DUT LO signal each passthrough directional couplers on the RFFE module. The coupled signals areeach mixed with the system local oscillator signal distributed by thelocal SG divider (from the CWSG6G on the RFCOM module) and downconvertedto base band where they can be digitized by the RBWD or other systemdigitizer. The directional coupler and mixer form the heart of the CMR,or Coupler-Mixer Receiver.

An optional noise source can be switched to the DUT Rx port for noisefigure testing.

The power detector and a loopback path near the output of the module aidin calibration and diagnostics.

5.4.2 Example RFFE Specifications TABLE 5.6 Example RFFE Specifications.Items Specification Conditions CMR Coupler Mixer Frequency Range 500MHz˜6 GHz Coupler- Input Power Level −70 dBm˜10 dBm At top of RF HifixMixer through RFMTX Receiver System Local Frequency Range 50 MHz˜6 GHz(with CWSG6G Frequency Resolution 1 Hz RBWD) RBWD Number of channels 2chBandwidth 35 MHz Sampling Frequency 100 MS/s Memory 32 MW/ch Number ofbits 14 bits5.4 RFMTX Module

The RFMTX module provides multiple Load Board connections for the inputsand outputs of the RFFE. This can greatly reduce Load Board componentcount and simplify layout.

5.4.1 RFMTX Description

FIG. 5.7 shows an exemplary block diagram of the RFMTX. Each RFMTXmodule can handle two RFFE modules. The switches on the RFMTX moduleconnect the RFFE DUT Rx port to one of four DUT input ports. Four DUToutput ports are switched to the DUT Tx port of the RFFE, while the DUTLO signal is switched between two DUT connections. Inactive connectionsare terminated in 50 ohms.

There are two optional switch types for the RFMTX module, coaxialmechanical relays or semiconductor switches. Semiconductor switchesprovide faster switching speeds, but are limited to 6 GHz bandwidth andhave more insertion loss. The coaxial mechanical relays provide 18 GHzbandwidth with less insertion loss, but at slower switching speeds.

5.4.2 Example RFMTX Specifications TABLE 5.7 Example RFMTXspecifications Con- Items Specification ditions RFMTX RF ports 2 DUTs;4: Tx, 4: Rx, 2: LO/DUT Semi- Bandwidth 20 MHz˜6 GHz conductor SwitchingTime 2 ms to 0.1 dB Switch Power handling 24 dBm Option +/−25 V DCLifetime infinite Impedance 50 ohms Coaxial Bandwidth DC˜18 GHzMechanical Switching Time 20 ms Relay Option Power handling 5 W (34dBm), Relay 0 V DC only Contact Life 5 million cycles Impedance 50 ohms5.5 RFPA Module

The RFPA module increases the VSG output power level specification. Thisis particularly useful for power amplifier testing.

5.6 RF Calibration

RF Calibration is performed on the RF modules as a complete instrunent.The calibration plane is the top of the RF HIFIX, at the blind mate RFconnectors. Normal calibration is performed at system determined fixedfrequencies. The calibration values at intermediate frequency points areinterpolated from the values at the nearest calibration frequencies.Focused calibration is available to provide greater accuracy atuser-defmed frequencies.

Calibration values are stored in a file on the site controller disk andare loaded into the RF hardware during init.

Calibration is performed using a Calibration Load Board and an externalpower meter, which provides NIST traceability.

5.7 Example Complete RF Instrument Specifications

Table 5.8 shows exemplary specifications for the RF Modules connectedtogether as a complete RF instrument. These specifications apply at theRF HIFIX, at the blind mate coaxial connectors that connect to the LoadBoard, after calibration. TABLE 5.8 Example Complete RF InstrumentSpecifications Item T2000 RF RF MTX RF Port 4: Tx, 4: Rx, 2: Lo SwitchOption Semiconductor Switch or Coaxial Mechanical Switch Switching Time2 mS@−0.1 dB Settled(Semi) 20 mS(Coaxial) CWSG6G Frequency Range 50MHz˜6 GHz Freq. Setting Resolution 1 Hz Output Power Level −70 dBm˜0 dBmLevel Setting Resolution 0.01 db Accuracy(after init/oinit) +−0.8 dB@−30dBm˜0 dBm Phase Noise −115 dBc/Hz@6 GHz, 100 KHz Offset Output Impedance50 ohm VSG/VSA VSG RF UPC Frequency ranges 50 MHz˜6 GHz Freq. SettingResolution 0.1 Hz Output Power level −120 dBm˜0 dBm(50 M˜2 GHz) −120dBm˜5 dBm(2 GHz˜6 GHz) Level Setting Resolution 0.01 dB Accuracy(afterinit/oinit) +−0.8 dB@−30 dBm˜0 dBm Phase Noise −115 dBc/Hz@6 GHz, 100KHz Offset Output Impedance 50 ohm RBWG Number of Channels 2 chFrequency ranges DC˜50 MHz Output Voltage >3 Vpp(T.B.D.) Anti-AliasingFilter THROUGH/2.5 MHz/50 MHz Sampling frequency 200 Msps Memory 64MW/ch Number of bits 14 bits VSG/VSA VSA RF DWC Frequency ranges 20MHz˜18 GHz(Coaxial SW) 50 MHz˜6 GHz(Semi SW) Input Power level −120dBm˜20 dBm Power Meas. Accuracy +−1 db@−30 dBm˜0 dBm (after init/oinit)Noise Floor −145 dBm/Hz typ RBWD Number of channels 2 ch Band width 35MHz Input Voltage >2 Vpp(T.B.D.) Sampling frequency 100 Msps Memory 32MW/ch Number of bits 14 bits Vecter Receiver Coupler Frequency ranges500 MHz˜6 GHz in RF Front End Mixer Input Power level −70 dBm˜10 dBmwith RBWD System Frequency Range 50 MHz˜6 GHz Local Freq. SettingResolution 1 Hz CWSG RBWD Number of channels 2 ch Band width 35 MHzInput Voltage >2 Vpp(T.B.D.) Sampling frequency 100 Msps Memory 32 MW/chNumber of bits 14 bits Test Capability Digital Communication standardGSM, cdma2000, WCDMA and Modulation 2 G 802.11b/a/g/h, HiperLAN2,HiSWANa Modulation GMSK, BPSK, QPSK, 16QAM, 64QAM, OFDM, CCK. . . etcDigital Modulation Analysis Spectrum, EVM, Constelletion chart Eyediagram . . .5.8 Parallel RF Testing

When multiple devices are tested in parallel, the device setup and RFinstrument setup for each test are done simultaneously for all the DUTs.RF signals are applied to all DUTs simultaneously. However, to reducesystem size and cost, signals received from the DUTs are digitized fromeach DUT sequentially. By utilizing the CMR Receiver (Coupler-MixerReceiver) for most tests, one can take advantage of fast electronicswitching to sequentially connect each DUT to the digitizer. At 100 MS/ssampling rate, digitizing 4K points takes about 40 microseconds. Thepenalty for digitizing sequentially at this rate for four DUTs is 3×40us=120 us, plus the overhead for switching. See the illustration in FIG.5.8.

6. BBFE Module

The BBFE or Base band Front End Module allows two channels of digitizerand two channels of AWG to test up to four DUTs in parallel (with 2channels of AWG and 2 channels of digitizer per DUT).

The BBFE is intended for use with the RBWG/D in the VSA/VSG module, orthe BBWG/D module.

6.1 BBFE Description

FIG. 6.1 shows an exemplary block diagram of the BBFE. The signals froma pair of AWGs are buffered and distributed to four sets of differentialoutput drivers, while the signals from four DUTs are likewise bufferedand sent to a pair of electronic switches that select one set of signalsto send on to a pair of digitizers. By rapidly sequencing the signalsfrom the four DUTs, the digitizers can sequentially digitize the signalsfrom all four DUTs. Usually at frequencies above audio, the actualdigitization time is small compared to the time spent setting up theDUTs and tester for a test, and performing other non-digitizing tests.Thus, only a small test time penalty is paid for savings in cost andtest head space.

Each of the four pairs of input and output buffers has its own DC offsetcontrol. Additionally, the four pairs of inputs and outputs aredifferential.

6.2 Example BBFE Specifications TABLE 6.1 Example BBFE SpecificationsItems Specification Conditions BBFE AWG Output type Differential outputNumber of differential 2 ch × 4 parallel ports section channelsImpedance 50 ohm SE; 100 ohm diff., +/−2% Coupling AC (0.01 uF), DCBandwidth (−3 dB) 100 MHz Amplitude ranges 500 mVpp to 2 Vpp Maximumoutput voltage −2 V to +2 V Maximum output current 20 mA Common mode DCoffset Per channel Offset range +/−2 V Offset resolution 0.5 mV Offsetsettling time 1 ms DGT Input type Differential input Number ofdifferential 2 ch × 4 selected port section channels ImpedanceSelectable 1M or 50 ohm SE; 2M or 100 ohm diff. Coupling AC (0.01 uF),DC Bandwidth (−3 dB) 100 MHz (50 ohm input) 30 MHz (1 Mohm input)Amplitude ranges +/−500 mV to +/−1.4 V Maximum input voltage −2.5 V to+2.5 V Prog. DC offset Per channel7. BBWG/D Module

The BBWG/D, or Base band Waveform Generator/Digitizer Module, is anarbitrary waveform generator and digitizer module intended for testingthe wide bandwidth base band signals used by Wireless LAN devices, aswell as for video band AC tests, Digital TV device testing, etc.

7.1 BBWG/D Description

FIG. 7.1 shows an exemplary block diagrarn of the BBWG/D. In addition toa pair of AWGs and digitizers, the module also provides two referencevoltage sources and PMU capability.

The AWGs have 16 bit resolution at up to 200 MS/s, while the digitizershave 12 bit resolution at up to 200 MS/s.

7.2 Example BBWG/D Specifications TABLE 7.1 Example BBWG SpecificationsItems Specification BBWG/D BBWG Sampling Rate 200 MS/s (max) Resolution16 bits Memory 1 MW/ch Number of 2 ch × 3 switch selected portsdifferential channels Output type Differential Impedance 50 ohm SE; 100ohm diff Bandwidth 70 MHz (−3 dB) Voltage range +/−125 mV to +/−2 VAnti-aliasing 20 MHz, 50 MHz filter DC linearity +/−0.1% of FSDistortion −70 dBc at 100 KHz to 5 MHz −65 dBc at 5 MHz to 10 MHz −50dBc at 10 MHz to 20 MHz −30 dBc at 20 MHz to 50 MHz

TABLE 7.2 Example BBWD Specifications Items Specification BBWG/D BBWDSampling Rate 200 MS/s (max) Resolution 12 bits Memory 512 KW × 2banks/ch Number 2 ch × 4 switch selected ports of differential channelsOutput type Differential Impedance Selectable 1M or 50 ohm SE; 2M or 100ohm diff. Bandwidth 70 MHz (50 ohm input) (−3 dB) 30 MHz (1M ohm input)Voltage range +/−350 mV to +/−2.5 V Anti-aliasing 20 MHz, 70 MHz andDigital filter Filter DC linearity +/−0.1% of FS Distortion −70 dBc at100 KHz to 5 MHz −65 dBc at 5 MHz to 10 MHz −50 dBc at 10 MHZ to 20 MHz8. AVWG Module

The AVWG/D, or Audio Video Waveform Generator/Digitizer Module, is anarbitrary waveform generator and digitizer module intended for low costtesting of audio and video devices. It also has high DC linearity,needed for certain types of DAC and ADC testing.

8.1 AVWG Description

FIG. 8.1 shows an exemplary block diagram of the AVWG/D. In addition toa pair of AWGs and digitizers, the module also provides two referencevoltage sources and PMU capability.

Each AWG has two sources, a low speed 16 bit resolution DAC that clocksat up to 1 MS/s, and a high speed 16 bit resolution DAC that clocks atup to 50 MS/s. The digitizers each have two ADCs, a 16 bit resolutionADC that can be clocked at up to 750 KS/s, and a 14 bit ADC that can beclocked at up to 50 MS/s.

8.2 Example AVWG Specifications TABLE 8.2 Example AVWD SpecificationsItems Specification AVWG/D AVWG Resolution/Sampling Rate 16 bit/1 MS/s16 bit/50 MS/s Memory 1 MW/ch Number of differential channels 2 ch × 3switch selected ports Output type Differential Impedance 50 ohm(+/−2%)or Low-Z SE; 100 ohm(+/−2%)or Low-Z diff; Coupling AC (0.01 uF), DCBandwidth (−3 dB) 200 KHz/20 MHz Voltage range +/−16 mV to +/−5 VAnti-aliasing filter 1 KHz, 1 MHz/15 MHz DC linearity +/−0.006% of FSDistortion −100 dBc at 1 KHz focused −80 dBc at 10 Hz to 100 KHz −68 dBcat 100 KHz to 1 MHz −60 dBc at 1 MHz to 5 MHz −50 dBc at 5 MHz to 10 MHzAVWG/D AVWD Resolution/Sampling Rate 16 bit/750 KS/s 14 bit/50 MS/sMemory 512 KW × 2 banks/ch Number of differential channels 2 ch × 4switch selected ports Output type Differential Impedance Selectable 1Mor 50 ohm SE; 2M or 100 ohm diff. +/−2% Bandwidth (−3 dB) 300 KHz/30 MHzVoltage range +/−125 mV to +/−5 V Anti-aliasing filter 100 KHz/20 MHz,and Digital Filter DC linearity +/−0.006% of FS Distortion −100 dBc at 1KHz focused −86 dBc at 10 Hz to 10 KHz −78 dBc at 10 KHz to 100 KHz −65dBc at 100 KHz to 1 MHz −53 dBc at 1 MHz to 5 MHz −50 dBc at 5 MHz to 10MHz9. Mixed-Signal Components of 250 MHz DM

The 250 MHz digital module can capture data from an A/D converter orother device that generates digital data representing an analogwaveform, and store that data for processing by mixed-signal analysistools (such as the FFT) To capture data in this fashion, the digitalmodule is used in the DCAP mode, or Digital CAPture mode. Each digitalpin (or channel) can operate in DCAP mode, but there are somerestrictions and memory limitations as noted in the tables below. Memoryfor digital pins that run from the same PG can be combined to providelarger memories for fewer numbers of pins.

The 250 MHz digital module can also be used to generate digital datarepresenting an analog waveform, such as might be used as the inputs toa D/A converter under test. This mode is called DAW, for DigitalArbitrary Waveform. In this mode, the SCAN memory is used to store DAWdata on a per channel basis. As in the DCAP mode above, memory size canbe traded off versus the number of active pins on a single PG, as notedin the tables below.

9.1 DCAP/DAW Description

FIG. 9.1 shows an exemplary block diagram of the 250M DM, highlightingthe DCAP and DAW memories.

9.2 Example DCAP/DAW Specification TABLE 9.1 Example DCAP SpecificationsItems Specification Conditions DCAP DCAP data source Compare LOW resultMemory size 2 Mbit/DM ch Channel link mode = normal 8 DCAP ch/PG max Maxch per domain = 1024 4 Mbit/DM ch Channel link mode = x2 4 DCAP ch/PGmax Max ch per domain = 512 8 Mbit/DM ch Channel link mode = x4 2 DCAPch/PG max Max ch per domain = 256 16 Mbit/DM ch Channel link mode = x8 1DCAP ch/PG max Max ch per domain = 128 Operating Frequency (Max} 250 MHzNormal Rate mode 500 MHz Double Rate mode Trigger mode Patternsynchronous or DUT output synch Trigger Continuous capture offset 0 to63 cycles Continuous capture 0 to 1023 cycles

TABLE 9.2 Example Maximum DCAP capture data Maximum DCAP Capture Data 1bit > 8 bit 1 bit > 16 bit 1 bit > 32 bit Normal mode 256K × 8 128K × 16 64K × 32 x2 mode 512K × 8 256K × 16 128K × 32 x4 mode 1M × 8 512K × 16256K × 32 x8 mode 2M × 8 1M × 16 512K × 32

TABLE 9.3 Example DAW Specifications Items Specification Conditions DAWDAW data SCAN memory source Memory size 128 Mbit/DM ch Channel link mode= normal 8 DAW ch/PG max Max ch per domain = 1024 256 Mbit/DM ch Channellink mode = x2 4 DAW ch/PG max Max ch per domain = 512 512 Mbit/DM chChannel link mode = x4 2 DAW ch/PG max Max ch per domain = 256 1 Gbit/DMch Channel link mode = x8 1 DAW ch/PG max Max ch per domain = 128 DataCache 250 MHz Normal Rate mode Operating 500 MHz Double Rate modeFrequency (Max} VGC frequency  50 MHz (max) Vector Address 250 MHzfrequency (max)10. RF and Analog Software

Software provides GUI tools for generating and analyzing waveforms, andfor setting and displaying the condition of the hardware. Softwaresupport is provided for shared resource parallel DUT testing, as well asRF test classes for OASIS. Calibration and diagnostic software are alsoprovided.

FIG. 10 shows an example of the configuration of a testing apparatus 100related to an exemplary embodiment of the present invention. The testingapparatus 100 includes a general controlling apparatus 102, sitecontrolling apparatuses 104, analog synchronization circuit controllingunits 106, digital synchronization controlling units 108, a plurality ofanalog testing modules 110 and a plurality of digital testing modules112. The plurality of analog and digital testing modules 110 and 112 arean example of the testing modules of the present invention.

The testing apparatus 100 generates and supplies test signals to thedevices under test 120, obtains the output signals outputted by thedevices under test 120 as a result of their operations in response tothe test signals, and judges the quality of the devices under test 120based on the output signals. The testing apparatus 100 uses modulesbased on an open architecture as the analog or digital testing module110 or 112 for supplying the test signal to the device under test 120.In other words, to a plurality of testing module slots, different typesof analog or digital testing modules 110 or 112 for generating differenttypes of test signals for the test of the devices under test 120respectively are optionally mounted.

The general controlling apparatus 102 obtains and stores a testcontrolling program, a testing program, test data, etc. used for thetest of the devices under test 120 via an external network. The sitecontrolling apparatus 104 controls the analog and digital testingmodules 110 and 112, and tests the plurality of devices under test 120in parallel at the same time. The connection relation between the sitecontrolling apparatus 104 and the analog and digital testing modules 110and 112 is changed corresponding to the number of pins of the deviceunder test 120, the wiring type of the performance board, the type ofthe analog and digital testing modules 110 and 112, etc. In other words,each of the plurality of site controlling apparatuses 104 performs adifferent test sequence in response to the performance of the devicesunder test 120 by dividing the plurality of analog and digital testingmodules 110 and 112 into plural sites, and controlling the operation ofthe analog or digital testing module 110 or 112 included in each site.

The site controlling apparatus 104 obtains and executes the testcontrolling program from the general controlling apparatus 102. And, thesite controlling apparatus 104 obtains the testing program and the testdata used in the test of the device under test 120 based on the testcontrolling program, and supply them to the analog or digital testingmodule 110 or 112 used in the test of each of the devices under test120. Then, the site controlling apparatus 104 instructs the analog ordigital testing module 110 or 112 to start the test based on the testingprogram and the test data by supplying the trigger signal and the clocksignal from the analog synchronization circuit controlling unit 106 tothe analog or digital testing module 110 or 112. And, the sitecontrolling apparatus 104 receives an interruption indicating the end ofthe test from the analog or digital synchronization controlling unit 106or 108, and informs the general controlling apparatus 102 of it.

The analog synchronization circuit controlling unit 106 controls thetest sequences by the analog testing modules 110 based on the control ofthe site controlling apparatus 104. For example, the analogsynchronization circuit controlling unit 106 supplies the analog testingmodule I10 with the trigger signal to start the test operation of thedevice under test 120 and the clock signal to control the testoperation, and receives the trigger return signal indicating thecompletion of the test operation of the analog testing module 110 fromthe analog testing module 110. In addition, the analog and digitalsynchronization controlling units 106 and 108 may hand over the triggerreturn signal to each other. For example, the digital synchronizationcontrolling unit 108 may hand over the trigger return signal receivedfrom the digital testirig module 112 to the analog synchronizationcircuit controlling unit 106, and the analog synchronization circuitcontrolling unit 106 may supply the trigger signal to the analog testingmodule 110 based on the trigger return signal received from the digitalsynchronization controlling unit 108.

Particularly, the analog synchronization circuit controlling unit 106has a function as operation order holding means of the presentinvention, so that it can hold the information indicating that the testoperation by a first testing module 110 among the plurality of analogtesting modules 110 should be performed before the test operation by afirst testing module 110 among the plurality of analog testing modules110. For example, the analog synchronization circuit controlling unit106 is set in advance by hardware before the test of the device undertest 120 begins in order to supply the trigger signal to the secondanalog testing module 110 when receiving the trigger return signal fromthe first analog testing module 110. And, the analog synchronizationcircuit controlling unit 106 has a function as trigger return signalreceiving means of the present invention and thus receives the triggerreturn signal indicating that the first analog testing module 110completes its test operation, when the test operation of the firstanalog testing module 110 has been finished, from the first analogtesting module 110. And, the analog synchronization circuit controllingunit 106 has a function as trigger supplying means of the presentinvention and thus supplies the second analog testing module 110 withthe trigger signal indicating that the second analog testing module 110should begin its test operation, when the trigger return signalreceiving means receives the trigger return signal.

In addition, if the analog testing module 110 performs different typesof testing operations in parallel for one or more devices under test120, the analog synchronization circuit controlling unit 106 may operatein the following manner. The analog synchronization circuit controllingunit 106 has a function as the operation order holding means.of thepresent invention and thus holds the information indicating that thefirst test operation by a first analog testing module 110 should beperformed before the test operation by a second analog testing module110, and the information indicating that the second test operation bythe first analog testing module 110 should be performed before the testoperation by the third analog testing module 110. And, the analogsynchronization circuit controlling unit 106 has a function as thetrigger return signal receiving means of the present invention and thusreceives a first trigger return signal indicating that the first analogtesting module 110 completes the first test operation, when the firsttest operation of the first analog testing module 110 has been finished,from the first analog testing module 110, and a second trigger returnsignal * indicating that the first analog testing module 110 completesthe second test operation, when the second test operation of the firstanalog testing module 110 has been finished, from the first analogtesting module 110. And, the analog synchronization circuit controllingunit 106 has a function as the trigger signal supplying means of thepresent invention and thus supplies the second analog testing module 110with a first trigger signal indicating that the second analog testingmodule 110 should begin its test operation, when the trigger returnsignal receiving means receives a first trigger return signal, andsupplies the third analog testing module 110 with a second triggersignal indicating that the third analog testing module 110 should beginits test operation, when the trigger return signal receiving meansreceives a second trigger return signal.

As above, according to the testing apparatus 100 related to thisembodiment, by supplying the trigger signal to a predetermined analogtesting module 110 based on the trigger return signal received from apredetermined analog or digital testing module 110 or 112 during testoperation, where the analog synchronization circuit controlling unit 106is set in advance by hardware, the predetermined analog testing module110 can start its operation, and a plurality of analog and digitaltesting modules 110 and 112 can operate in a desired order. Accordingly,although the analog and digital testing modules 110 and 112 mounted tothe plurality of testing module slots are optionally changed, it ispossible to reduce the work required to make the test programcorresponding to the mounting positions or the combination of thetesting modules, and to curtail the time required to test the devicesunder test. Further, the digital synchronization controlling unit 108may control the test operation of the digital testing module 112 byfunctioning as the analog synchronization circuit controlling unit 106described above.

FIG. 11 shows an example of the detailed configuration of the testingapparatus 100 related to this embodiment. The testing apparatus 100includes an arbitrary waveform adjustor 110 a and a phasecharacteristics tester 110 b as the analog testing module 110, and apattern generator 112 a as the digital testing module 112. The analogsynchronization circuit controlling unit 106 includes reference clockgenerating unit 200, a variable clock generating unit 202, a clockmatrix 204, and a trigger matrix 206.

The arbitrary waveform adjustor 110 a generates and supplies anarbitrary analog waveform to the device under test 120 based on thecontrol of the analog synchronization circuit controlling unit 106. Inaddition, the phase characteristics tester 110 b receives the analogwaveform outputted by the device under test 120 in response to theanalog waveform supplied from the arbitrary waveform adjustor 110 a, andtests the phase characteristics of the analog waveform. The arbitrarywaveform adjustor 110 a and the phase characteristics tester 110 b havePLL (Phase Locked Loop) circuits, and operate while generating internalclocks based on the reference clock generated by the reference clockgenerating unit 200. The pattern generating unit 112 a sets the deviceunder test 120 by generating and supplying a digital pattern to thedevice under test 120 based on the control of the digitalsynchronization controlling unit 108.

The clock matrix 204 is set with respect to hardware in advance beforethe test of the device under test 120, so that the connections of theinput and the output are determined. In other words, which clock signalfrom the variable clock generating unit 202, the digital synchronizationcontrolling unit 108, the performance board, etc. is supplied to thearbitrary wavefom adjustor 110 a or the phase characteristics tester 110b is determined. In addition, the trigger matrix 206 is set with respectto hardware in advance before the test of the device under test 120, sothat the connections of the input and the output are determined. Inother words, when a trigger return signal from any of the arbitrarywaveform adjustor 110 a, the phase characteristics tester 110 b, thepattern generator 112 a, etc. is received, which the arbitrary waveformadjustor 110 a or the phase characteristics tester 110 b the triggersignal is supplied to is deterrnined.

That is, the trigger matrix 206 has a function as the operation orderholding means of the present invention, and thus holds the informationindicating that the supply operation of the arbitrary waveform adjustor110 a to the device under test 120 should be performed before thereceiving operation of the phase characteristics tester 110 b from thedevice under test 120. And, the trigger matrix 206 has a function as thetrigger return signal receiving means, and thus receives a triggerreturn signal indicating that the arbitrary waveform adjustor 110 acompletes its supply operation, when the arbitrary waveform adjustor 110a has finished the supply operation of the analog waveform at apredetermined time, from the arbitrary waveform adjustor 110 a. And, thetrigger matrix 206 has a function as the trigger signal supplying means,and thus supplies a trigger signal indicating that the phasecharacteristics tester 110 b should begin its operation to receive theanalog waveform from the device under test 120, when the trigger returnsignal receiving means has received the trigger return signal, to thephase characteristics tester 110 b.

As above, by sequentially controlling the operations of the arbitrarywaveform adjustor 110 a and the phase characteristics tester 110 bthrough receiving and sending the trigger return signal and the triggersignal, although there occurs a delay in applying the analog waveform tothe device under test 120 by the arbitrary waveform adjuster 110 a, thephase characteristics tester 110 b does not start to receive the analogwaveform as long as there occurs no trigger return signal from thearbitrary waveform adjustor 110 a, whereby there isn't any disorder inthe test sequences to allow the phase characteristics tester 110 b tostart to receive the analog waveform before the arbitrary waveformadjustor 110 a finishes applying the analog waveform, while thearbitrary waveform adjustor 110 a and the phase characteristics tester110 b can be operated in a proper order and with proper timing.

FIG. 12 shows an example of the operation sequence of the testingapparatus 100 related to this embodiment. First, the reference clockgenerating unit 200 makes the arbitrary waveform adjustor 110 a and thephase characteristics tester 110 b capable of operating by applying thereference clock to the arbitrary waveform adjustor 110 a and the phasecharacteristics tester 110 b. At this time, the arbitrary waveformadjustor 110 a is in a wait state for a start signal as an example ofthe trigger signal, and the phase characteristics tester 110 b is in await state for the trigger signal.

Then, the pattern generator 112 a generates and supplies a digitalpattern to the device under test 120 based on the control of the digitalsynchronization controlling unit 108, and sets up the device under test120. The pattern generator 112 a turns into the wait state when theset-up of device under test 120 is completed. Meanwhile, when the startsignal is supplied to the. arbitrary waveform adjustor 110 a from thedigital synchronization controlling unit 108 via the trigger matrix 206,the arbitrary waveform adjustor 110 a generates the analog waveformstored in a pattern memory, and starts to supply the device under test120. And, the arbitrary waveform adjustor 110 a supplies a marker signalas an example of the trigger return signal to the trigger matrix 206,when finishing its supply operation at a predetermined time of theanalog waveform to the device under test 120. The trigger matrix 206supplies the trigger signal to the phase characteristics tester 110 b,when receiving the marker signal from the arbitrary waveform adjustor110 a.

And, the phase characteristics tester 110 b receives the analog waveformoutputted from the device under test 120 in response to the analogwaveform supplied from the arbitrary waveform adjustor 110 a, whenreceiving the trigger signal from the trigger matrix 206. The phasecharacteristics tester 110 b supplies a capture end signal as an exampleof the trigger signal to the trigger matrix 206, when finishing thereceiving operation of the analog waveform outputted from the deviceunder test 120. And, the trigger matrix 206 supplies a continue signalto the digital synchronization controlling unit 108, when receiving thecapture end signal from the phase characteristics tester 110 b. Thedigital synchronization controlling unit 108 allows the patterngenerator 112 a to generate a new digital signal and set up the deviceunder test 120, when receiving the continue signal. The patterngenerator 112 a turns into the wait state, when the set-up of the deviceunder test 120 is finished. In addition, the digital synchronizationcontrolling unit 108 supplies an advance signal as an example of thetrigger signal, when receiving the capture end signal from the triggermatrix 206. The trigger matrix 206 supplies the advance signal as anexample of the trigger signal to the arbitrary waveform adjustor 110 a,when receiving the advance signal from the digital synchronizationcontrolling unit 108.

And, the arbitrary waveform adjustor 110 a switches the analog waveformby generating the next analog waveform stored in the pattern memory andstarts to supply the device under test 120, when receiving the advancesignal from the trigger matrix 206. As above, by sequentially repeatingthe set-up operation of the pattern generator 112 a, the supplyoperation of the arbitrary waveform adjustor 110 a, and the receivingoperation of the phase characteristics tester 110 b, the output waveformof the device under test 120 is received by the phase characteristicstester 110 b in response to each of the plurality of different analogwaveforms. And, the phase characteristics tester 110 b generates aninterruption to the site controlling apparatus 104 and informs that thetest sequence is finished, when a predetermined number of outputwaveforms have been received. And, the site controlling apparatus 104stops the arbitrary waveform adjustor 110 a supplying the analogwaveform to the device under test 120, stops the digital synchronizationcontrolling unit 108 operating, and stops the pattern generator 112 asupplying the digital pattern to the device under test 120. And, thesite controlling apparatus 104 stops the reference clock generating unit200 supplying the reference clock to the arbitrarywaveform adjustor 110a and the phase characteristics tester 110 b.

As above, the trigger matrix 206 performs receiving and sending withregard to the start signal, the marker signal, the trigger signal, thecapture end signal, the continue signal, or the advance signal from andto the arbitrary waveform adjustor 110 a, the phase characteristicstester 110 b, the pattern generator 112 a, or the digitalsynchronization controlling unit 108 based on the predetermined hardwareset-up. Accordingly, the testing apparatus 100 in this embodiment canoperate the arbitrary waveform adjustor 110 a, the phase characteristicstester 110 b, and the pattern generator 112 a in a desired order basedon the testing program where the operation order of the arbitrarywaveform adjustor 110 a, the phase characteristics tester 110 b, and thepattern generator 112 a is not determined.

FIG. 13 shows an example of the configuration of the trigger matrix 206related to this embodiment. The trigger matrix 206 includes a pluralityof trigger controlling modules 400. Each of the trigger controllingmodules 400 includes a multiplexer circuit 402, a priority encoder 404,and a flip-flop circuit 406. Each of the trigger controlling modules 400is coupled to the plurality of analog testing modules 110 respectivelysuch as the arbitrary waveform adjustor 110 a and the phasecharacteristics tester 110 b, and supplies the trigger signal to each ofthe plurality of analog testing modules in response to the suppliedtrigger return signal.

First, the hardware set-up of the trigger controlling module 400 beforethe test of the device under test 120 begins will be described. When astatus signal is supplied to the trigger controlling module 400 by atleast one of trigger return signal sources based on an instruction ofthe site controlling apparatus 104, the priority of encoder 404 receivessignals supplied from the plurality of trigger return signals via aplurality of interfaces respectively, and calculates and supplies thestatus information indicating which trigger return signal sourcesupplies the status signal to the flip-flop circuit 406. And, when anenable signal is supplied to the flip-flop circuit 406 by the arbitrarywaveform adjustor 110 a based on an instruction of the site controllingunit 104, and a set-up request signal is supplied from the sitecontrolling unit 104 to the flip-flop circuit 406, the flip-flop circuit406 holds the status information being supplied from the priorityencoder 404 when the set-up request signal is supplied as a selectsignal for controlling the multiplexer circuit 402 to select the controlsignal based on the set-up request signal. Accordingly, the hardwareset-up of the trigger controlling module 400 is performed, and theconnections of the input and the output are determined. Here, as thetrigger return signal sources, there is the digital synchronizationcontrolling unit 108, the arbitrary waveform adjustor 110 a, the phasecharacteristics tester 110 b, the performance board, etc.

Next, the operation of the trigger controlling module 400 during thetest of the device under test 120 will be described. The flip-flopcircuit 406 supplies the status information held before the start of thetest as described above to the multiplexer circuit 402 as the selectsignal. And, the multiplexer circuit 402 is functioning as the triggerreturn signal receiving means of the present invention, and obtains aplurality of trigger return signals supplied from each of the pluralityof trigger return signal sources based on an instruction of the sitecontrolling apparatus 104. And, the multiplexer circuit 402 isfunctioning as the trigger signal supplying means of the presentinvention, and selects the trigger return signal obtained from each ofthe trigger return signal sources, a plurality of trigger returnsignals, the digital synchronization controlling unit 108 or the phasecharacteristics tester 110 b based on the select signal supplied fromthe flip-flop circuit 406, and supplies it to the arbitrary waveformadjustor 110 a as the trigger signal.

According to the trigger controlling module 400 related to thisembodiment, before the start of the test of device under test 120, thepriority encoder 404 generates status information, and the flip-flopcircuit 406 holds it as the select signal, whereby the hardware set-upof the trigger controlling module 400 is performed, and the test can beperformed by properly selecting the trigger signal source in response tothe arbitrary waveform adjustor 110 a and the phase characteristicstester 110 b.

Although the present invention has been described by way of exemplaryembodiments, it should be understood that those skilled in the art mightmake many changes arid substitutions without departing from the spiritand the scope of the present invention which is defined only by theappended claims.

1. A testing apparatus which comprises a plurality of testing moduleslots to which different types of testing modules for testing a deviceunder test are optionally mounted, comprising: operation order holdingmeans for holding information indicating that a test operation by afirst testing module among said plurality of testing modules should beperformed before a test operation by a second testing module among saidplurality of testing modules; trigger return s ignal receiving means forreceiving a trigger return signal from said first testing module, saidtrigger return signal indicating that said first testing module hascompleted said test operation thereof, when said test operation of saidfirst testing module has been completed; and trigger signal supplyingmeans for supplying a trigger signal to said second testing module, saidtrigger signal indicating that said second testing module should startsaid test operation thereof, when said trigger return signal receivingmeans receives said trigger return signal.
 2. A testing apparatus asclaimed in claim 1, wherein said first testing module is an arbitrarywaveform adjustor for generating and supplying an arbitrary analogwaveform to said device under test, said second testing module is aphase characteristics tester for receiving an analog waveform outputtedby said device under test in response to said analog waveform suppliedfrom said arbitrary waveform adjustor, and testing phase characteristicsof said analog waveform, said operation order holding means holdsinformation indicating that said phase characteristics tester shouldperform a receiving operation of said analog waveform from said deviceunder test, after said arbitrary waveform adjustor performs a supplyoperation of said analog waveform to said device under test, saidtrigger return signal receiving means receives said trigger returnsignal from said arbitrary waveform adjustor, said trigger return signalindicating that said arbitrary waveform adjustor has completed saidsupply operation, when said supply operation at a predetermined time ofsaid analog waveform has completed by said arbitrary waveform adjustor,and said trigger signal supplying means supplies said trigger signal tosaid phase characteristics tester, said trigger signal indicating thatsaid phase characteristics tester should start said receiving operationof said analog waveform from said device under test, when said triggerreturn signal receiving means receives said trigger return signal.
 3. Atesting apparatus as claimed in claim 1, wherein said trigger returnsignal receiving means and said trigger signal supplying means are amultiplexer circuit for obtaining each of a plurality of said triggerreturn signals from each of said plurality of testing modules, selectingone of said trigger return signals obtained from said first testingmodule, and supplying said selected trigger return signal to said secondtesting module as said trigger signal, and said operation order holdingmeans is a flip-flop circuit for holding a select signal for controllingsaid multiplexer circuit to select said trigger return signal.
 4. Atesting apparatus as claimed in claim 1, wherein said first testingmodule performs first and second test operations in parallel, saidoperation order holding means holds information indicating that saidtest operation by said second testing module should be performed aftersaid first test operation by said first testing module, and informationindicating that a test operation by a third testing module among saidplurality of testing modules should be performed after said second testoperation by said first testing module, said trigger return signal meansreceives a first trigger return signal from said first testing module,said first trigger return signal indicating that said first testingmodule has completed said first test operation, when said first testoperation of said first testing module has been completed, and a secondtrigger return signal from said first testing module, said secondtrigger return signal indicating that said first testing module hascompleted said second test operation, when said second test operation ofsaid first testing module has been completed, and said trigger signalsupplying means supplies a first trigger signal to said second testingmodule, said first trigger signal indicating that said second testingmodule should start said test operation thereof, when said triggerreturn signal receiving means receives said first trigger return signal,and a second trigger signal to said third testing module, said secondtrigger signal indicating that said third testing module should startsaid test operation thereof, when said trigger return signal receivingmeans receives said second trigger return signal.